1. Field of the Disclosure
The present disclosure relates to a semiconductor circuit.
2. Description of the Related Art
In order to design chips that operate at high speed, designs of a high-speed flip-flop and a high-speed clock gating circuit (or a clock gate) are important. Although existing D latch-based flip-flops and clock gating circuits occupy small areas and consume relatively little power, there are limitations due to a data-to-output latency (DQ latency) that is relatively too slow to be applied to the high-speed chip.